Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor

An automatic routing method for automatic placement and global routing of integrated circuits on an integrated circuit chip, comprising:

• floor plan processing for placing macro cells and for determining a region in which basic cells are to be placed;
• basic cell placement processing;
• global routing processing for dividing said integrated circuit chip into a plurality of global routing cells and determining a route of each net in each global routing cell based on a degree of wire congestion at each global routing cell boundary and a grid use rate at each global routing cell;
• and
• detailed routing processing for determining a detailed route within each global routing cell.

An automatic routing method for automatic placement and global routing of integrated circuits on an integrated circuit chip, comprising:

• dividing said logic circuit chip into a plurality of global routing cells;
• calculating a wire capacity of each global routing cell boundary, the wire capacity indicating how many wires can pass through each global routing cell boundary;
• calculating a number of grids usable for routing in each global routing cell;
• and
• determining a route of every net such that the cost is minimized based on said wire capacity and said grid use rate representing a ratio of a number of grids to be used divided by the number of useable grids.

A computer readable memory storing a control program for controlling an automatic routing which automatically places and wires integrated circuits on an integrated circuit chip, said control program comprising:

• floor plan processing for placing macro cell and for determining a region in which basic cells are to be placed;
• basic cell placement processing;
• global routing processing for dividing said integrated circuit chip into a plurality of global routing cells and determining a route of each net at each global routing cell based on a degree of wire congestion at each global routing cell boundary and a grid use rate at each global routing cell;
• and
• detailed routing processing for determining a detailed route within each global routing cell.

A computer readable memory storing a control program for controlling an automatic routing which automatically places and wires integrated circuits on an integrated circuit chip, said control program comprising:

• dividing said logic circuit chip into a plurality of global routing cells;
• calculating a wire capacity of each global routing cell boundary, the wire capacity indicating how many wires can pass through each global routing cell boundary;
• calculating a number of grids usable for routing in each global routing cell;
• and
• determining a route of every net such that the cost is minimized based on said wire capacity and said grid use rate representing a ratio of a number of grids to be used divided by the number of useable grids.