Time switching circuit of synchronous super high speed transmission apparatus and controlling method thereof

Abstract

A memory saving type time switching circuit of a synchronous super high speed transmission apparatus for saving required memory by switching data based on data properties being received by a synchronous super high speed transmission apparatus. A frame information signal generating portion receives data that is to be switched and generates count signals for data switching. A record control portion stores received data to a switching memory portion according to received data type using a predetermined rule. According to received data types and switching information from the central processing unit, a connection information generator reads the switching memory portion using a predetermined rule. According to read data types from the switching memory portion, an output time point compensation portion compensates an output point. In the present invention, saving of required memories for data switching by considering data properties and optimizing system structure and operation by treating data switching in one board are possible.

Dependencies are inferred from the claim text.