US 6,377,070 B1 · In-service programmable logic arrays with ultra thin vertical body transistors

Abstract

Structures and methods for in-service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in-service programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. At least one single crystalline ultra thin vertical floating gate transistor that is disposed adjacent each vertical pillar. The single crystalline vertical floating gate transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A vertical floating gate opposes the ultra thin single crystalline vertical body region.

Claims77

Dependent claims

An in-service programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function;
and
wherein each of the logic cells includes;
a vertical pillar extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
at least one single crystalline ultra thin vertical floating gate transistor that is selectively disposed adjacent the vertical pillar, wherein each single crystalline vertical floating gate transistor includes;
an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
and
a floating gate opposing the ultra thin single crystalline vertical body region.

9 more elements

A programmable logic array, comprising:

a plurality of input lines for receiving an input signal;
a plurality of output lines;
and
one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
a vertical pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
a pair of single crystalline ultra thin vertical transistors formed along opposing sides of the pillar, wherein each single crystalline vertical transistor includes;
an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
and
an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
wherein a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;
and
a floating gate opposing the ultra thin single crystalline vertical body region, and wherein the floating gate is formed in a trench between rows of the number of pillars and is shared between the ultra thin single crystalline vertical floating gate transistors that are adjacent the trench in column adjacent pillars;
a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array;
and
wherein each of the number of input lines is disposed between rows of the pillars and opposes the floating gates of the single crystalline vertical floating gate transistors for serving as a control gate.

13 more elements

A low voltage programmable logic array, comprising:

a number of input lines for receiving an input signal;
a number of output lines;
and a first logic plane that receives a number of input signals on the number of input lines, the first logic plane having a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
a second logic plane coupled to the first logic plane by a number of interconnect lines, the second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function;
wherein each logic cell includes:
a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
a number of single crystalline ultra thin vertical transistors formed along selected sides of each pillar, wherein each single crystalline vertical transistor includes;
an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
and
a floating gate opposing the vertical body region and separated therefrom by a tunnel oxide;
a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of column adjacent pillars in the array.

11 more elements

An electronic system, comprising:

a memory;
a processor coupled to the memory;
and
wherein the processor includes at least one in service programmable logic array including:
a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
and
wherein each of the logic cells includes;
a vertical pillar extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
at least one single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar, wherein each single crystalline vertical transistor includes;
an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
and
a floating gate opposing the vertical body region and separated therefrom by a tunnel oxide.

13 more elements

An electronic system, comprising:

a memory;
a processor coupled to the memory;
and
wherein the processor includes at least one programmable logic array including:
a number of input lines for receiving an input signal;
a number of output lines;
and
one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a number of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
a vertical pillar extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
a number of single crystalline ultra thin vertical transistor that are disposed adjacent the vertical pillar, wherein each single crystalline vertical transistor includes;
an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
and
an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
and
a floating gate opposing the vertical body region and separated therefrom by a tunnel oxide.

14 more elements

An electronic system, comprising:

a memory;
a processor coupled to the memory;
and
wherein at least one of the processor and memory include a programmable logic array including:
a number of input lines for receiving an input signal;
a number of output lines;
a first logic plane that receives a number of input signals on the number of input lines, the first logic plane having a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
a second logic plane coupled to the first logic plane by a number of interconnect lines, the second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function;
wherein each logic cell includes:
a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
a number of single crystalline ultra thin vertical transistors formed along selected sides of each pillar, wherein each single crystalline vertical transistor includes;
an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
and
a floating gate formed in a trench opposing the vertical body region and separated therefrom by a gate oxide;
a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array.

15 more elements

A method for forming a programmable logic array, comprising:

forming a first logic plane that receives a number of input signals, wherein forming the first logic plane includes forming a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
forming a second logic plane, wherein forming the second logic plane includes forming a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
and
wherein forming each of the logic cells includes;
forming a vertical pillar extending outwardly from a semiconductor substrate, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer of a first conductivity type separated by an oxide layer;
and
forming a single crystalline ultra thin vertical transistor that is disposed adjacent the vertical pillar, wherein forming the single crystalline vertical transistor includes;
depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
and
wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by a body region formed of the single crystalline vertically oriented material of the second conductivity type;
and
forming a floating gate opposing the vertical body region and separated therefrom by a gate oxide.

10 more elements

A method for forming a programmable logic array, comprising:

forming a plurality of input lines for receiving an input signal;
forming a plurality of output lines;
and
forming one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein forming the first logic plane and the second logic plane includes forming a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein forming each logic cell includes:
forming a pillar extending outwardly from a semiconductor substrate, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
forming a single crystalline ultra thin vertical transistor which is disposed adjacent the vertical pillar, wherein forming the single crystalline vertical transistor includes;
depositing a lightly doped polysilicon layer of a second conductivity type over each pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
and
wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by a body region formed of the single crystalline vertically oriented material of the second conductivity type;
and
forming a floating gate opposing the vertical body region and separated therefrom by a gate oxide.

10 more elements

A method of forming a low voltage programmable logic array, comprising:

forming a number of input lines for receiving an input signal;
forming a number of output lines;
forming a first logic plane that receives a number of input signals on the number of input lines, wherein forming the first logic plane includes forming a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
forming a second logic plane coupled to the first logic plane by forming a number of interconnect lines, wherein forming the second logic plane includes forming a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function;
wherein forming each logic cell includes;
forming a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer separated by an oxide layer;
and
forming a pair of single crystalline ultra thin vertical transistors on opposing each pillar, wherein forming each single crystalline vertical transistor includes;
depositing a lightly doped polysilicon layer of a second conductivity type over each pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
and
wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by a body region formed of the single crystalline vertically oriented material of the second conductivity type;
and
forming a floating gate opposing the vertical body regions and separated therefrom by a gate oxide;
and
forming a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array.

13 more elements

Dependencies are inferred from the claim text.

In-service programmable logic arrays with ultra thin vertical body transistors

Life of this patent

In-service programmable logic arrays with ultra thin vertical body transistors

Life of this patent

Abstract

Claims77