Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects

A method for fabricating wire bond pads for applications in MOSFET and CMOS semiconductor devices using copper dual damascene, a method comprising:

• providing a substrate, wafer or substrate module;
• providing a first level of conducting wiring being defined and over said substrate;
• depositing a passivating layer over the first level of conducting wiring;
• depositing a first insulating layer of dielectric, forming a first intermetal dielectric layer (IMD), over the passivating layer;
• depositing a second insulating layer of dielectric, forming a second intermetal dielectric layer (IMD), over the first insulating layer of dielectric (IMD);
• patterning and etching the intermetal dielectric layers (IMD), and said passivating layer, forming a dual damascene trench/via opening, exposing regions of the first level of conducting wiring;
• depositing and patterning a cap layer over the second intermetal dielectric layer (IMD);
• depositing a first blanket conductive metal barrier layer or first barrier layer, over the patterned cap layer, and into the trench/via openings, and over said exposed regions of the first level of conducting wiring;
• depositing a blanket copper layer over the first barrier layer, and filling the trench/via openings;
• polishing back by chemical mechanical polishing (CMP) the excess copper and first barrier layer material, stopping on the cap layer, forming a dual damascene inlaid copper interconnect trench/via;
• forming a photoresist over the inlaid copper and cap layer;
• patterning the photoresist making an exposed opening over a portion of the inlaid copper;
• etching back by wet etching the top layer of the exposed portion of the inlaid copper within the trench/via, forming a partially recessed copper region or portion within the trench/via and forming a partially recessed trench/via opening;
• stripping the photoresist by oxygen plasma ashing or solvent stripper;
• etching copper oxide on the top layer of the copper in the recessed copper region within the trench/via, that may be present, by hydrogen or ammonia plasma gas treatment;
• depositing a second blanket conductive metal barrier layer or second barrier layer, over said copper and said recessed copper region within the trench/via, and over the patterned cap layer;
• depositing a blanket layer of Al—Cu alloy over the second barrier layer, and filling the partially recessed trench/via opening;
• annealing thermally with forming gas the layer of Al—Cu alloy, enhancing alloy formation;
• polishing back by chemical mechanical polishing (CMP) the Al—Cu alloy and second barrier layer material, stopping on the cap layer, forming a centrally located region of inlaid Al—Cu alloy bond pad, over a copper dual damascene interconnect trench/via, suitable for wire bonding and soldering without further passivation.

A method for fabricating wire bond pads for applications in MOSFET and CMOS semiconductor devices using copper dual damascene, a method comprising:

• providing a substrate, wafer or substrate module;
• providing a first level of conducting wiring being defined and over said substrate;
• depositing a first passivating layer over the first level of conducting wiring;
• depositing a first insulating layer of dielectric, forming a first intermetal dielectric layer (IMD), over the first passivating layer;
• depositing a second insulating layer of dielectric, forming a second intermetal dielectric layer (IMD), over the first insulating layer of dielectric (IMD);
• patterning and etching the intermetal dielectric layers (IMD), and said passivating layer, forming a dual damascene trench/via opening, exposing regions of the first level of conducting wiring;
• depositing a first blanket conductive metal barrier layer or first barrier layer, into the trench/via openings, and over said exposed regions of the first level of conducting wiring;
• depositing a blanket copper layer over the first barrier layer, and filling the trench/via openings;
• polishing back by chemical mechanical polishing (CMP) the excess copper and first barrier layer material, stopping on the second intermetal dielectric layer (IMD), forming dual damascene inlaid copper interconnect trench/via;
• depositing a second passivating layer or top passivating layer over the inlaid copper and over the second intermetal dielectric layer (IMD);
• forming a photoresist over the inlaid copper and top passivating layer;
• patterning the photoresist making an exposed opening over a portion of the inlaid copper;
• etching by reactive ion etch (RIE) the exposed second passivating layer or top passivating layer, exposing the top layer of the inlaid copper within the trench/via;
• etching back by reactive ion etching (RIE) or wet etching back the top layer of the exposed portion of the inlaid copper within the trench/via, forming a partially recessed copper region or portion within the trench/via and forming a partially recessed trench/via opening;
• stripping the photoresist by oxygen plasma ashing or solvent stripper;
• etching copper oxide on the top layer of the copper in the recessed copper region within the trench/via, that may be present, by hydrogen or ammonia plasma gas treatment;
• depositing a second blanket conductive metal barrier layer or second barrier layer, over the partially recessed copper region, or recess copper, within the trench/via, and over the patterned second passivation layer or top passivation layer;
• depositing a blanket layer of Al—Cu alloy over the second barrier layer, and filling the partially recessed trench/via opening;
• annealing thermally with forming gas the layer of Al—Cu alloy, enhancing alloy formation;
• polishing back by chemical mechanical polishing (CMP) the Al—Cu alloy and second barrier layer material stopping on said second passivating layer or top passivating layer, forming a centrally located region of inlaid Al—Cu alloy bond pad, over a copper dual damascene interconnect trench/via, suitable for wire bonding and soldering without further passivation.