Determining error locations using error correction codes

A method of operating a computation circuit in a decoder, the method comprising:

• operating the computation circuit in a first mode to produce syndrome values in response to a first set of inputs;
• operating the computation circuit in a second mode to produce location values in response to a second set of inputs, the second set of inputs corresponding to coefficients of an error locator polynomial;
• wherein operating the computation circuit in the second mode comprises using r computation stages to compute greater than r location values;
• and
• wherein the error locator polynomial is of a degree t and wherein using the r computation stages further comprises computing a different one of the r location values in a corresponding one of the r computation stages during t+1 clock cycles.

A method of operating a computation circuit in a decoder, the method comprising:

• operating the computation circuit in a first mode to produce syndrome values in response to a first set of inputs;
• operating the computation circuit in a second mode to produce location values in response to a second set of inputs, the second set of inputs corresponding to coefficients of an error locator polynomial;
• comparing the computed location values to a zero value;
• and
• if the computed location values are equal to a zero value, indicating that an error locator polynomial root from which an error location may be obtained has been found.

An apparatus, comprising:

• a computation circuit;
• and
• a control unit for enabling the computation circuit to operate in either a first mode or a second mode;
• the computation circuit being adapted to compute syndrome values in response to a first set of inputs in the first mode;
• and
• the computation circuit being adapted to compute location values in response to a second set of inputs in the second mode.

An apparatus, comprising:

• a computation circuit;
• a control unit for enabling the computation circuit to operate in either a first mode or a second mode;
• the computation circuit being adapted to compute syndrome values in response to a first set of inputs in the first mode;
• the computation circuit being adapted to compute location values in response to a second set of inputs in the second mode;
• wherein the computation circuit includes r parallel computation stages;
• wherein the computation circuit computes r location values for the second set of inputs when enabled to operate in the second mode;
• and
• wherein the error locator polynomial is of a degree t and wherein the computation circuit computes a different one of the r location values in a corresponding one of the r parallel computation stages during t+1 clock cycles.