Integrated LAN controller and web server chip

A network controller for a device, the device including a host processor, the controller comprising:

• a media access controller for accepting packets having unique first and second destination addresses;
• a buffer for temporarily buffering the packets accepted by the media access controller;
• a host interface;
• a dedicated processor programmed to function as a web server, the dedicated processor being further programmed to determine the destination addresses of packets in the buffer, route the packets having the first destination address to the dedicated processor, and route the packets having the second destination address to the host processor;
• flash memory including a first plurality of executable instructions and a second plurality of executable instructions, the first plurality of instructions, when executed, instructing the dedicated processor to function as the web server, the second plurality of instructions, when executed, instructing the dedicated processor to read the destination addresses of packets in the buffer and route the packets;
• a DRAM for storing the packets having the first destination address;
• and
• a memory interface for the Flash memory and the DRAM.