Method and arrangement in a transposed digital FIR filter for multiplying a binary input signal with tap coefficients and a method for designing a transposed digital filter

A multiplication apparatus to multiply a binary number by a fractional coefficient comprising:

• a receiving and retention means to acquire and retain said binary number;
• a shifting means connected to receiving and retention means to shift said binary number bit-wise toward a least significant bit;
• a decomposing means to determine a sum of a plurality of fractional binary numbers that constitute said fractional coefficient;
• a binary digit selector to select binary digit locations of the binary number from said shifting means, whereby said selected binary digit locations represent fractional binary numbers;
• a combining means connected to the binary digit selector to arithmetically combine the contents of the binary digit locations from binary digit selector to form a single binary digit of a result of said multiplication;
• and
• a transferring means connected to the combining means and the shifting means to transfer said single binary digit of the result for further processing and to cause said shifting means to shift said binary number by one binary digit to generate each successive digit of said result.

A multiply/accumulate apparatus to perform a matrix multiplication of a matrix of binary numbers with a vector of fractional coefficients comprising:

• a multiplication unit that comprises:
• a receiving and retention means to acquire and retain one of said binary numbers,
• a shifting means connected to receiving and retention means to shift said binary number bit-wise toward a least significant bit,
• a decomposing means to determine a sum of a plurality of fractional binary numbers that constitute said fractional coefficient,
• a binary digit selector to select binary digit locations of the binary number from said shifting means, whereby said selected binary digit locations represent fractional binary numbers,
• a combining means connected to the binary digit selector to arithmetically combine the contents of the binary digit locations from binary digit selector to form a single binary digit of a result of said multiplication, and
• a transferring means connected to the combining means and the shifting means to transfer said single binary digit of the result for further processing and to cause said shifting means to shift said binary number by one binary digit to generate each successive digit of said result.