Digitally self-calibrating circuit and method for pipeline ADC

In a pipeline ADC including a plurality of stages including an input stage and a first group of sequentially coupled subsequent stages,

• the input stage including a unity gain amplifier having an input for receiving an analog input signal, an output, and a first comparator having a first input coupled to the output of the unity gain amplifier and a second input for receiving a first reference voltage and an output,
• each subsequent stage including an amplifier having an input and an output, a summer having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output, a switching circuit operating in response to the outputs of a comparator of a previous stage to selectively couple one of a second reference voltage and a third reference voltage to a second input of the summer, a first comparator having a first input coupled to the output of the summer the first comparator of the subsequent stage having a second input for receiving the first reference voltage and an output,
• the improvement comprising:
• a second comparator in the input stage, the second comparator having a second input for receiving a second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator of the input stage, a second input coupled to the output of the second comparator of the input stage, and an output producing MSB bit information;
• and
• each subsequent stage including a second comparator, the second comparator of the subsequent stage having a first input coupled to the output of the summer, the second comparator of the subsequent stage having a second input for receiving the second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator of the subsequent stage and a second input coupled to the output of the second comparator of the subsequent stage,
• the full adder of each subsequent stage producing bit information less significant than the MSB bit information.

A pipeline ADC comprising a plurality of stages including an input stage and a first group of sequentially coupled subsequent stages,

• the input stage including a unity gain amplifier having an input for receiving an analog input signal, an output, and at least first and second comparators each having a first input coupled to the output of the unity gain amplifier, the first comparator having a second input for receiving a first reference voltage and an output, the second comparator having a second input for receiving a second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information;
• and
• each subsequent stage including an amplifier having an input and an output, a summer having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output, a digital-to-analog conversion circuit having a plurality of inputs coupled to outputs of first and second comparators of a previous stage, the digital-to-analog conversion circuit having an output coupled to a second input of the summer to convert the outputs of the first and second comparators of the previous stage to a third reference voltage, a fourth reference voltage, or a fifth reference voltage applied to the second input of the summer, at least first and second comparators each having a first input coupled to the output of the summer, the first comparator of the subsequent stage having a second input for receiving the first reference voltage and an output, the second comparator of the subsequent stage having a second input for receiving the second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator of the subsequent stage, a second input coupled to the output of the second comparator of the subsequent stage, the full adder producing bit information less significant than the MSB bit information.

A method of operating a pipeline ADC including a plurality of stages including an input stage and a first group of sequentially coupled subsequent stages, comprising:

• applying an analog input signal to an input of a unity gain amplifier in the input stage to produce an output signal;
• applying the output signal of the unity gain amplifier to a first input of at least first and second comparators;
• applying a first reference voltage to a second input of the first comparator and applying a second reference voltage to a second input of the second comparator, outputs of the first and second comparators representing MSB bit information of the pipeline ADC;
• applying the output signal of the unity gain amplifier to an input of an amplifier of a first subsequent stage;
• applying an output signal of the amplifier of the first subsequent stage to a first input of a summer;
• applying the outputs of the first and second comparators to a digital-to-analog converting circuit in the first subsequent stage to convert the outputs of the first and second comparators to a converted signal equal to one of a third reference voltage, a fourth reference voltage, and fifth reference voltage and applying the converted signal to a second input of the summer;
• applying an output signal of the summer to a first input of each of a first and a second comparator of the first subsequent stage;
• applying the first reference voltage to a second input of the first comparator of the first subsequent stage and applying a second reference voltage to a second input of the second comparator of the first subsequent stage, outputs of the first and second comparators of the first subsequent stage representing less significant bit information of the pipeline ADC.

A self-calibrating pipeline ADC comprising a plurality of analog-to-digital conversion units and a recursive calibrating section operable for calibrating errors associated with an immediately preceding first conversion unit wherein the recursive calibrating section includes a first circuit for receiving an analog output signal generated from the first conversion unit in response to an analog input signal provided to the first conversion unit, a second circuit for receiving a digital output signal generated from the first conversion unit in response to a digital input signal provided to the first conversion unit, a third circuit for generating a conversion signal corresponding to a quantized representation of the analog output signal, and a fourth circuit for generating a calibration signal having a value equal to the conversion signal in response to the digital input signal having a first digital value, having a value equal to the sum of the conversion signal and a first calibration value in response to the digital input signal being a second digital value, and having a value equal to the difference between the conversion signal and a second calibration value in response to a third digital value, wherein

• the pipeline ADC includes a first group of successively coupled bit stages including an input stage and a first group of subsequent stages,
• the input stage including a unity gain amplifier having an input for receiving an analog input signal, an output, and at least first and second comparators each having a first input coupled to the output of the unity gain amplifier, the first comparator having a second input for receiving a first reference voltage and an output, the second comparator having a second input for receiving a second reference voltage and an output, and a fall adder having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information;
• and
• each subsequent stage including an amplifier having an input and an output, a summer having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output, a switching circuit operating in response to the outputs of first and second comparators of a previous stage to selectively couple one of a third reference voltage, a fourth reference voltage, and fifth reference voltage to a second input of the summer, at least first and second comparators each having a first input coupled to the output of the summer, the first comparator of the subsequent stage having a second input for receiving the first reference voltage and an output, the second comparator of the subsequent stage having a second input for receiving the second reference voltage and an output, and a full adder having a first input coupled to the output of the first comparator of the subsequent stage, a second input coupled to the output of the second comparator of the subsequent stage, the full adder producing bit information less significant than the MSB bit information.