Circuit and method for preventing runaway in a phase lock loop
AssigneeCypress Semiconductor Corporation
InventorsSen-Jung Wei, Kuang-Yu Chen
Life of this patent
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Abstract
A circuit and/or method comprising an oscillator circuit, a pulse detection circuit and a control circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The pulse detection circuit may be configured to generate a detect signal in response to the output signal. The control circuit may be configured to generate the second control signal in response to said detect signal.
Claims14
An apparatus comprising:
- an oscillator circuit configured to generate an output signal having a frequency in response to (i) a first control signal generated in response to a reference signal and said output signal and (ii) a second control signal;
- a pulse detection circuit comprising an edge detector circuit, configured to generate a detect signal in response to said output signal by detecting edges in a feedback signal;
- and
- a control circuit configured to generate said second control signal in response to said detect signal by timing the spacing of said edges.
An apparatus comprising:
- an oscillator circuit configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal;
- a pulse detection circuit comprising an integrator and a hysteresis circuit, configured to generate a detect signal in response to said output signal by detecting edges in a feedback signal;
- and
- a control circuit configured to generate said second control signal in response to said detect signal by timing the spacing of said edges.
An apparatus comprising:
- means for generating an output signal having a frequency in response to (i) a first control signal generated in response to a reference signal and said output signal and (ii) a second control signal;
- means for generating a detect signal, comprising an edge detector circuit, in response to said output signal by detecting edges in a feedback signal;
- and
- means for generating said second control signal in response to said detect signal by timing the spacing of said edges.
A method of preventing a runaway condition in a phase lock loop comprising the steps of:
- (A) generating an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal;
- (B) generating a detect signal in response to said output signal by (i) detecting edges in a feedback signal and (ii) timing the spacing of said edges;
- and
- (C) generating said second control signal in response to said detect signal.
Dependencies are inferred from the claim text.