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US 6,366,529 B1Granted
Fast FiFo memory storage system
AssigneeTexas Instruments Incorporated
InventorsKenneth L. Williams, Rakesh N. Joshi
Life of this patent
Estimating the term…
Abstract
A fast FIFO memory system stores identical data in both static RAM memory and FIFO memory. Data is transferred from the FIFO when insufficient RAM read time is available. When the FIFO is full, additional data is stored in the RAM which runs at a much slower speed than the FIFO. Data is then transferred from the RAM until the FIFO is no longer full, at which time the memory system again functions at the faster FIFO speed.
Claims14
A FIFO memory storage system comprising:
- a plurality of RAM memory storage elements;
- a write ring-counter operatively coupled to the plurality of RAM memory storage elements and operative to communicate with the plurality of RAM memory storage elements such that data words can be selectively written into the plurality of RAM memory storage elements;
- a read ring-counter operatively coupled to the plurality of RAM memory storage elements and operative to communicate with the plurality of RAM memory storage elements such that data words can be selectively read from the plurality of RAM memory storage elements;
- a data selector operatively coupled to the read ring-counter and the plurality of RAM memory storage elements;
- a data output register;
- and
- a multiplexer operatively coupled to the plurality of RAM memory storage elements, the data selector and the data output register and operative to selectively transfer data from the plurality of RAM memory storage elements to the data output register via the data selector.
4 more elements
A FIFO memory storage system comprising:
- a plurality of RAM memory storage elements, each RAM memory storage element including a dual port RAM portion and a FIFO portion;
- a write ring-counter operatively coupled to the plurality of RAM memory storage elements and operative to communicate with the plurality of RAM memory storage elements such that data words and associated address data can be selectively written into each dual port RAM portion and each FIFO portion;
- a read ring-counter operatively coupled to the plurality of RAM memory storage elements and operative to communicate with the plurality of RAM memory storage elements such that data words can be selectively read from each dual port RAM portion and each FIFO portion;
- a data selector operatively coupled to the read ring-counter and the plurality of RAM memory storage elements;
- a data output register;
- and
- a multiplexer operatively coupled to the plurality of RAM memory storage elements, the data selector and the data output register and operative to selectively transfer data from a FIFO portion to the data output register via the data selector when the total FIFO capacity has not been exceeded and to selectively transfer data from RAM portion to the data output register via the data selector when the total FIFO capacity has been exceeded.
4 more elements
A FIFO memory storage system comprising:
- a plurality of static RAM memory storage elements;
- a plurality of FIFO memory storage elements;
- a memory control element in communication with the plurality of static RAM memory storage elements and the plurality of FIFO memory storage elements, wherein the memory control element is operative to cause data to be read from the plurality of FIFO memory storage elements when data stored by the FIFO memory storage system must be available before a static RAM memory read cycle can be completed;
- a write ring-counter operatively coupled to the plurality of static RAM memory storage elements and plurality of FIFO memory storage elements and operative to communicate with the plurality of static RAM memory storage elements and plurality of FIFO memory storage elements such that data words and associated address data can be selectively written into each static RAM memory storage element and each FIFO memory storage element;
- a read ring-counter operatively coupled to the plurality of static RAM memory storage elements and plurality of FIFO memory storage elements and operative to communicate with the plurality of static RAM memory storage elements and the plurality of FIFO memory storage elements such that data words can be selectively read from each static RAM memory storage element and each FIFO memory storage element;
- a data selector operatively coupled to the read ring-counter and the plurality of static RAM memory storage elements and plurality of FIFO memory storage elements;
- a data output register;
- and
- a multiplexer operatively coupled to the plurality of static RAM memory storage elements, the plurality of FIFO memory storage elements, the data selector and the data output register, wherein the multiplexer is operative to selectively transfer data from a FIFO memory storage element to the data output register via the data selector when the total FIFO memory storage element capacity has not been exceeded and to selectively transfer data from a static RAM memory storage element to the data output register via the data selector when the total FIFO memory storage element capacity has been exceeded.
6 more elements
Dependencies are inferred from the claim text.