US 6,366,174 B1 · Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking

Abstract

An improved clock generation circuit is provided that operates with a single input clock frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder. If a periodic modulation is desired, the address look-up table will point to add amounts that create a particular periodic output frequency profile, which could include a Spread Spectrum profile. Certain optional circuits may be included, such as: a pre-multiply or pre-divide circuit to either increase or decrease the frequency of the input clock signal before it reaches the phase/frequency detector of the PLL; an output divider to provide a lower output clock frequency; a feedback divider to lower the VCO's output frequency before it is directed into the digital accumulator; a synchronizing input (Sync Input); a synchronizing output (Sync Output); a Base Number register to keep the memory size of the look-up table to a reasonably small value; or a Start Number register to provide the add amount upon initialization.

Claims18

Dependent claims

A clock generating circuit, comprising:

(a) a frequency synthesizer circuit having:
(i) an error detector, (ii)an oscillator output circuit, and (iii) a feedback loop that includes an adder circuit;
(b) said frequency synthesizer circuit receiving:
(i) an input clock signal of a substantially constant frequency, which is in communication with said error detector, and (ii) an add/phase quantity which is in communication with said adder circuit, wherein said add/phase quantity is varied in a periodic manner, thereby causing an output frequency to change in a periodic manner;
(c) said adder circuit having a single bit output that is in communication with said error detector, said output acting as a modulated feedback clock signal, wherein said modulated feedback clock signal comprises a pulse signal that is generated at substantially equal time intervals per count sequence of said adder circuit and that is derived from one of (i) a Carry bit, or (ii) a most Significant Bit of said adder circuit;
(d) at least one latch circuit that temporarily holds an output valve of said adder circuit, and thereby creates said modified feedback clock signal;
and
wherein said frequency synthesizer circuit generates a substantially accurate output frequency under control of said add/phase quantity, and wherein said add/phase quantity is generated by an Add Amount Modulator circuit, which comprises:
(i) an address look-up table, and (ii) a memory circuit that stores various add amount numeric quantities;
wherein said memory circuit provides a varying numeric quantity to said adder circuit over time.

7 more elements

Dependencies are inferred from the claim text.

Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking

Life of this patent

Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking

Life of this patent

Abstract

Claims18