PNP high-current, high-swing output stage and method

An amplifier output stage comprising:

• a first PNP transistor having a collector coupled to an amplifier output and an emitter coupled to a first power supply rail and a base;
• a second NPN transistor having a base for receiving an input signal and
• a collector coupled to a base of the first PNP transistor;
• and
• a bias circuit configured to produce a thevenin equivalent bias voltage having an associated output impedance, with the bias circuit coupled to the base of the first PNP transistor and including a third PNP transistor and a first resistor connected relative to the third PNP transistor such that the equivalent bias voltage is equal to a difference in a base-emitter voltage of the third PNP transistor and a voltage drop across the first resistor, with the bias equivalent voltage having a magnitude which is smaller than a magnitude of the base-emitter voltage.

A method of biasing an amplifier output stage having a first PNP transistor with an emitter coupled to a power supply rail and a collector coupled to an output of the amplifier output stage and a frequency compensation capacitor coupled to the first PNP transistor, said method comprising:

• generating a base-emitter voltage using a second transistor;
• generating a first voltage having a magnitude that is relatively independent of current flow in the first PNP transistor;
• combining the base-emitter voltage and the first voltage to produce a bias voltage equal to a difference between the base-emitter voltage and the first voltage so that the bias voltage has a magnitude smaller than a magnitude of the base-emitter voltage;
• and
• coupling the bias voltage through an effective output impedance across the base-emitter junction of the first PNP transistor.

An amplifier output stage of an amplifier, said output stage comprising:

• a first PNP transistor having a collector coupled to an amplifier output and an emitter coupled to a first power supply rail;
• a second NPN transistor having a base for receiving an input signal and a collector coupled to a base of the first PNP transistor;
• a first frequency compensation capacitor having one terminal coupled to the collector of the first PNP transistor;
• and
• a bias circuit coupled to the first PNP transistor and configured to provide a therein equivalent bias voltage having an associated output impedance, with the bias circuit coupled to a base of the first PNP transistor so that the first PNP transistor will conduct a desired quiescent current, with said bias circuit being disposed outside a signal path defined by the base and collector of the second NPN transistor and the base and collector of the first PNP transistor and with the output impedance being sufficiently large to form a pole in combination with the first frequency compensation capacitor at a frequency beyond a unity-gain frequency of the amplifier.