Buffer circuit having Schottky gate transistors adjusting amplitude of output signal
AssigneeOki Electric Industry Co., Ltd.
InventorHiroyuki Yamada
Life of this patent
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Abstract
A buffer circuit having an input and output terminals includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.
Claims5
A buffer circuit having input and output terminals, comprising
- a first Schottky gate transistor connected between a voltage setting node and ground;
- a load device connected between a power supply and the voltage setting node;
- a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node;
- a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal;
- and
- a resistor means connected between the gate of the first Schottky gate transistor and the input terminal for applying a voltage level, which is a sum of a clamp voltage of the first Schottky gate transistor and the product of a resistance value of the resistor means and a current passing through the resistor means, to the gate of the third Schottky gate transistor.
Dependencies are inferred from the claim text.