Multi-bit-cell non-volatile memory with maximized data capacity

A memory comprising:

• a plurality of memory units, each memory unit comprising:
• a memory array;
• a write circuit that receives an Nmax-bit value and programs a threshold voltage of a memory cell in the array, to a target level selected according to the Nmax-bit value;
• and
• a read circuit that generates an Nmax-bit value according to a threshold voltage of a memory cell being read;
• a global data bus coupled to provide Nmax-bit values to the write circuits and receive Nmax-bit values from the read circuits;
• and
• input/output circuitry coupled to the global data bus, the input/output circuitry selecting a number of bits on the global data bus that are actual data, the number of bits depending on which of the plurality of memory units is involved in a data transfer on the global data bus.

A memory comprising:

• a plurality of memory units;
• a global write/read circuit coupled to the plurality of memory units to control writing to and reading from the plurality of memory units;
• input/output circuitry coupled to the global write/read circuit, the input/output circuitry selecting a number of bits of actual data transferred by a write or read operation, the number of bits depending on which of the plurality of memory units is the target of the write or read operation;
• and
• a converter coupled to the global write/read circuit, wherein
• the converter converts a first digital signal to an analog signal representing a value for a write operation that the global write/read circuit controls, the digital signal containing a number of data bits selected by the input/output circuitry;
• and
• the converter converts an analog signal from the global write/read circuit to a second digital signal, the second digital signal containing a number of data bits selected by the input/output circuitry.

A memory comprising:

• a plurality of memory units;
• a global write/read circuit coupled to the plurality of memory units to control writing to and reading from the plurality of memory units;
• input/output circuitry coupled to the global write/read circuit, the input/output circuitry selecting a number of bits of actual data transferred by a write or read operation, the number of bits depending on which of the plurality of memory units is the target of the write or read operation;
• and
• a configuration register coupled to the input/output circuitry, the configuration register containing configuration values indicating for each memory unit, a number of data bits stored per memory cell in that memory unit.

A method for using an integrated circuit memory, comprising:

• selecting a first memory array in the integrated circuit memory;
• identifying a number N1 of bits per cell for the first memory array;
• accessing a first selected memory cell in the first memory array, wherein the access of the first selected memory cell transfers N1 bits of data;
• selecting a second memory array in the integrated circuit memory;
• identifying a number N2 of bits per cell for the second memory array, wherein N2 differs from N1;
• and
• accessing a second selected memory cell in the second memory array, wherein the access of the second selected memory cell transfers N2 bits of data.