CMOS latch and register circuitry using quantum mechanical tunneling structures
AssigneeTexas Instruments Incorporated
InventorXiaowei Deng
Life of this patent
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Abstract
CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).
Claims10
A CMOS semiconductor latch device comprising:
- tunneling structure latch circuitry;
- a complementary pass gate data input circuitry, directly connected to said tunneling structure circuitry and adapted to pass data to said tunneling structure latch circuitry;
- and
- data output circuitry, coupled to said tunneling structure latch circuitry, and adapted to output data received therefrom.
A CMOS semiconductor register device comprising:
- a first tunneling structure latch circuit;
- complementary pass gate data input circuitry, directly connected to said first tunneling structure latch circuit and adapted to pass data to said first tunneling structure latch circuit;
- a second tunneling structure latch circuit;
- data transmission circuitry, coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit;
- and
- data output circuitry, coupled to said second tunneling structure latch circuit, and adapted to output data received therefrom.
Dependencies are inferred from the claim text.