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US 6,362,652 B1Granted
High voltage buffer for submicron CMOS
AssigneeFujitsu Microelectronics Limited
InventorsMustafa Ertugrul Oner, Sumer Can
Life of this patent
Estimating the term…
Abstract
An input circuit allows input buffers fabricated using submicron CMOS technologies to receive input signals having a voltage swing of 5V. The input circuit uses a cascode transistor to bias the drain of the input transistor so that the VGD of the input transistor does not reach or exceed the gate-oxide breakdown voltage. Outputs of the input buffers have a maximum voltage that is limited by their respective supply voltages.
Claims26
An integrated circuit comprising:
- an input transistor receiving an input signal having a voltage swing of a first range of voltages, the maximum of the first range of voltages being greater than or equal to a gate-oxide breakdown voltage of the input transistor;
- a bias transistor coupled to the input transistor, the bias transistor controlling internal voltage differences of the input transistor to be within a second range of voltages, the maximum of the second range or voltages being less than the gate-oxide break down voltage of the input transistor;
- and
- a reference current source coupled to the bias transistor,
- wherein the bias transistor is coupled between the input transistor and the reference current source.
2 more elements
A buffer circuit comprising:
- a charge down circuit receiving an input signal, the charge down circuit being used to generate a charge down signal to pull down an output of the buffer circuit to logic low:
- a charge up circuit receiving the input signal, the charge up circuit being used to generate a charge up signal to pull up the output of the buffer circuit to logic high;
- and
- a current source circuit coupled to the charge down circuit and the charge up circuit, the current source circuit providing reference currents to the charge down circuit and the charge up circuit,
- wherein the charge up circuit provides the charge up signal when the voltage level of the input signal is higher than a trip voltage, and the buffer circuit further comprises a charge up transistor wherein the charge up signal turns on the charge up transistor to pull up the output of the buffer circuit to logic high.
2 more elements
A buffer circuit comprising:
- a charge down circuit receiving an input signal, the charge down circuit being used to generate a charge down signal to pull down an output of the buffer circuit to logic low;
- a charge up circuit receiving the input signal, the charge up circuit being used to generate a charge up signal to pull up the output of the buffer circuit to logic high;
- and
- a current source circuit coupled to the charge down circuit and the charge up circuit, the current source circuit providing reference currents to the charge down circuit and the charge up circuit,
- wherein the charge down circuit comprises an input transistor receiving the input signal and a cascode transistor receiving a bias voltage, and wherein the bias voltage is selected to limit internal voltages of the input transistor to stay below a gate-oxide breakdown voltage of the input transistor.
2 more elements
A buffer circuit comprising:
- a charge down circuit receiving an input signal, the charge down circuit being used to generate a charge down signal to pull down an output of the buffer circuit to logic low;
- a charge up circuit receiving the input signal, the charge up circuit being used to generate a charge up signal to pull up the output of the buffer circuit to logic high;
- and
- a current source circuit coupled to the charge down circuit and the charge up circuit, the current source circuit providing reference currants, to the charge down circuit and the charge up circuit,
- wherein the charge up circuit comprises an input transistor receiving the input signal and a cascode transistor receiving a bias voltage, and wherein the bias voltage is selected to limit internal voltages of the input transistor to stay below a gate-oxide breakdown voltage of the input transistor.
2 more elements
A buffer circuit comprising:
- a charge down circuit receiving an input signal, the charge down circuit being used to generate a charge down signal to pull down an output of the buffer circuit to logic low;
- a charge up circuit receiving the input signal, the charge up circuit being used to generate a charge up signal to pull up the output of the buffer circuit to logic high;
- and
- a current source circuit coupled to the charge down circuit and the charge up circuit, the current source circuit providing reference currents to the charge down circuit and the charge up circuit,
- wherein the charge down circuit provides the charge down signal when a voltage level of the input signal is lower than a trip voltage, and the buffer circuit further comprises a charge down transistors wherein the charge down signal turns on the charge down transistor to pull down the output of the buffer circuit to logic low.
2 more elements
A buffer circuit comprising:
- a charge down circuit receiving an input signal, the charge down circuit being used to generate a charge down signal to pull down an output of the buffer circuit to logic low;
- a charge up circuit receiving the input signal, the charge up circuit being used to generate a charge up signal to pull up the output of the buffer circuit to logic high;
- and
- a current source circuit coupled to the charge down circuit and the charge up circuit, the current source circuit providing reference currents to the charge down circuit and the charge up circuit,
- wherein the buffer circuit is a class-AB push-pull buffer circuit fabricated using submicron CMOS technologies.
2 more elements
A method of providing a high voltage input signal to an integrated circuit comprising:
- providing the high voltage input signal at a gate of an input transistor;
- coupling the input transistor to a bias transistor;
- and
- providing a selected bias voltage to the bias transistor to limit voltages within the input transistor to be less than a gate-oxide breakdown voltage for the input transistor;
- wherein the bias transistor is coupled between the input transistor and a reference current source.
2 more elements
Dependencies are inferred from the claim text.