Circuitry to provide fast carry

A circuit for providing a carry operation comprising:

• a first multiplexer having a first input for receiving a carry in (C), a second input, and a select input, the first multiplexer comprising:
• a first transistor having a source to drain path coupling the first input of the first multiplexer to the output of the first multiplexer, and having a gate coupled to the select input of the first multiplexer;
• a second transistor having a source to drain path coupling the second input of the first multiplexer to the output of the first multiplexer, and having a gate;
• and
• a first inverter coupling the select input of the first multiplexer to the gate of the second transistor;
• a first look up table having a first input for receiving a first signal (A), a second input for receiving a second signal (B) and an output coupled to the select input of the first multiplexer;
• a second multiplexer having a first input for receiving the carry in (C), a second input coupled for receiving an inverse of the carry in, a select input coupled to the output of the first look up table, and an output providing a sum (S);
• and
• a second inverter coupling the output of the first multiplexer to a carry input of the second multiplexer.

A circuit for providing a carry operation comprising:

• a first look up table having a first input for receiving a first signal (A), a second input for receiving a second signal (B) and an output;
• a second look up table having a first input for receiving the first signal (A), a second input for receiving the second signal (B) and an output;
• a first multiplexer having a first input coupled to the output of the first look up table, a second input coupled to the output of the second look up table, and a select input;
• a first gate having a first input for receiving a third signal (D), a second input for receiving an enable signal (f) and an output coupled to the select input of the first multiplexer, the first gate functioning to provide the third signal D to the select input of the third first multiplexer when the enable signal (f) is active, and to not provide the third signal D to the select input of the first multiplexer when the enable signal is inactive;
• and
• a second multiplexer having a first input for receiving a carry in (C), a second input coupled to the output of the second look up table, a select input coupled to the output of the first look up table, and an output coupled for providing a carry out.

A circuit for providing a carry operation comprising:

• a first look up table having a first input for receiving a first signal (A), a second input for receiving a second signal (B) and an output;
• a second look up table having a first input for receiving the first signal (A), a second input for receiving the second signal (B) and an output;
• a first multiplexer having a first input for receiving a carry in (C), a second input coupled to the output of the second look up table, a select input coupled to the output of the first look up table, and an output coupled for providing a carry out;
• and
• a second multiplexer having a first input for receiving the carry in (C), a second input coupled for receiving an inverse of the carry in, a select input coupled to the output of the first look up table, and an output providing a sum (S).

A circuit for providing a carry operation comprising:

• a look up table having a first input for receiving a first signal (A), a second input for receiving a second signal (B) and an output;
• a first multiplexer having a first input for receiving a carry in (C), a second input coupled to receive the firs signal A, a select input coupled to the output of the look up table, and an output coupled for providing a carry out;
• and
• a second multiplexer having a first input for receiving the carry in (C), a second input coupled for receiving an inverse of the carry in, a select input coupled to the output of the look up table, and an output providing a sum (S).