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US 6,356,105 B1Granted
Impedance control system for a center tapped termination bus
AssigneeIntel Corporation
InventorAndrew M. Volk
Life of this patent
Estimating the term…
Abstract
A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.
Claims27
A method comprising:
- comparing an output potential of a buffer with a pair of reference potentials;
- generating a result from said comparison;
- storing said result for later evaluation;
- and
- adjusting output impedance of said buffer to cause said output voltage swing to match said reference potentials.
2 more elements
An apparatus comprising:
- a first comparator to compare an output of a buffer and a first reference voltage;
- control state machine logic coupled to said first comparator, said state machine logic to evaluate an output of said first comparator;
- adjustment logic coupled to said state machine logic, said adjustment logic to alter output impedance of said buffer;
- and
- an adjustable impedance device coupled to said adjustment logic, said impedance device varying according to inputs from said adjustment logic.
2 more elements
An integrated circuit device comprising:
- a data pad;
- an output buffer coupled to said data pad, said output buffer to provide an output voltage to said pad;
- and
- an impedance control mechanism coupled to said output buffer, said mechanism comprising:
- a first comparator to compare a pad voltage and a first reference voltage;
- control state machine logic coupled to said first comparator, said state machine logic to evaluate an output of said first comparator;
- adjustment logic coupled to said state machine logic, said adjustment logic to alter output impedance of said buffer;
- and
- an adjustable impedance device coupled to said adjustment logic, said impedance device varying according to inputs from said adjustment logic.
6 more elements
A system comprising:
- a bus;
- a first integrated circuit device coupled to said bus, said first integrated circuit comprising:
- an output buffer coupled to a data pad, said output buffer providing an output voltage to said pad;
- and
- an impedance control mechanism coupled to said output buffer, said mechanism comprising:
- a first comparator to compare a pad voltage and a first reference voltage;
- control state machine logic coupled to said first comparator, said state machine logic to evaluate an output of said first comparator;
- adjustment logic coupled to said state machine logic, said adjustment logic to alter output impedance of said buffer;
- and
- an adjustable impedance device coupled to said adjustment logic, said impedance device varying according to inputs from said adjustment logic;
- and
- a second integrated circuit device coupled to said bus, said second integrated to receive a data signal from said first integrated circuit device.
9 more elements
Dependencies are inferred from the claim text.