Method for operating non-volatile memory cells
AssigneeAMIC Technology Corporation
InventorsKou-Su Chen, Shih-Chun Fu, Jui-Te Chan
Life of this patent
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Abstract
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
Claims20
A method of operating flash memory cells in a flash memory cell array, the method including the steps of:
- (a) placing such flash memory cells into a programmed state;
- and
- (b) modifying electrical charge on floating gates of the flash memory cells while they are in said programmed state by applying a partial erase signal adapted to be substantially lower in intensity than a full strength erase signal;
- and
- (c) repeating step (b) for a number of pulses n so as to ensure that a threshold voltage of all of said flash memory cells is below a target threshold voltage value, and said flash memory cells have approximately equal erase rates;
- (d) applying an erase signal for a second number of pulses N (where N>>n) to such flash cells so as to place such cells in a fully erased state.
A method of operating flash memory cells in a flash memory cell array, the method including the steps of:
- (a) programming such flash memory cells into a programmed state;
- and
- (b) performing a pre-erase operation on such flash memory cells while they are in said programmed state, said pre-erase operation including:
- i) configuring a partial erase signal to have a magnitude that is less than or equal to a full erase signal;
- ii) applying said partial erase signal n times to all of said flash memory cells during a first time period, where said first time period and n are adapted so as to not place such flash memory cells into a fully erased state;
- iii) repeating step ii) as needed for selected flash memory cells so that a threshold voltage of all of said flash memory cells is below a target threshold voltage value, and so that all of said flash memory cells have approximately equal erase rates;
- wherein during step iii) at least said magnitude of said partial erase signal is adjusted;
- (c) performing an erase operation as to place such cells in a fully erased state.
Dependencies are inferred from the claim text.