US 6,353,403 B1 · Fast ramping of control voltage with enhanced resolution

Abstract

A logic circuit for generating a control voltage includes a ramp DAC and a main DAC. When the control voltage is needed, such as when an associated crystal oscillator is being “turned on,” an input reference voltage is supplied to both the ramp DAC and the main DAC. The ramp DAC generates an output based on the input reference voltage and L supplied control bits for a (preferably short) ramp time period. The output from the ramp DAC is fed to a filter circuit that includes a capacitor to charge the capacitor and the control voltage is generated at least in part from the ramp DAC output as filtered by the capacitor. When the ramp period ends, the state of the input reference voltage is changed and the output from the main DAC, based on the changed input reference voltage and N control bits, is input to the filter. Such a two DAC arrangement allows for a shorter time constant circuit to be employed in association with the ramp DAC and a longer time constant circuit to be employed in association with the main DAC, allowing for quick ramp up of the control voltage.

Claims22

Dependent claims

A method of generating a control voltage from a logic circuit having a first digital to analog converter having L bit control and a second digital to analog converter having N bit control, wherein L is less than N, said method comprising the steps of:

generating a control voltage signal based on output from said first digital to analog converter for a first time period;
said output from said first digital to analog converter based on an input voltage reference signal having a first state;
and
changing the state of said input voltage reference signal from said first state to a second state and generating said control voltage signal based on output from said second digital to analog converter;
said output from said second digital to analog converter based on said input voltage reference signal in said second state.

2 more elements

sleeping said first digital to analog converter and said second digital to analog converter;
thereafter, awakening said first digital to analog converter and supplying an input voltage reference signal having a first state and L control bits to said first digital to analog converter;
producing an output from said first digital to analog converter based on said first state of said voltage reference signal and said L control bits for a first time period;
awakening said second digital to analog converter;
after said first time period expires, changing the state of said input voltage reference signal to a second state;
and
supplying said input voltage reference signal having said second state and N control bits to said second digital to analog converter and producing an output from said second digital to analog converter based on said second state of said voltage reference signal and said N control bits;
deriving a control voltage based at least on said output from said first digital to analog converter during said first time period and based on at least said output from said second digital to analog converter during a second time period after said first time period.

5 more elements

A control voltage generating circuit, comprising:

a first digital to analog converter with L bit control;
a second digital to analog converter with N bit control connected in parallel with said first digital to analog converter;
wherein L is less than N;
a filter connected to said first digital to analog converter and said second digital to analog converter;
said filter including a capacitor and having an output;
a voltage reference signal supplied to both said first digital to analog converter and said second digital to analog converter, said voltage reference signal having at least a first state and a second state;
said filter output varying sequentially between at least the following three modes:
i) a first mode wherein said filter output is based on said first digital to analog converter and said voltage reference signal having said first state;
ii) a second mode wherein said filter output is based on said second digital to analog converter and said voltage reference signal having said second state;
iii) a sleep mode wherein said filter output is substantially zero,
said capacitor charging faster in said first mode than in said second mode.

8 more elements

Dependencies are inferred from the claim text.

Fast ramping of control voltage with enhanced resolution

Life of this patent

Fast ramping of control voltage with enhanced resolution

Life of this patent

Abstract

Claims22