US 6,352,917 B1Granted

Reversed damascene process for multiple level metal interconnects

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsSubhash Gupta, Mei-Sheng Zhou, Simon Chooi, Sangki Hong

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Abstract

A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.

Claims34

Dependent claims

A method to form metal interconnect levels in the manufacture of an integrated circuit device comprising:

depositing a first dielectric layer overlying a semiconductor substrate wherein said semiconductor substrate comprises all layers and devices formed prior to said depositing of said first dielectric layer and wherein said first dielectric layer may comprise a stack of dielectric materials;
patterning said first dielectric layer to form trenches for planned damascene interconnects;
depositing an insulating layer overlying said first dielectric layer and lining said trenches;
anisotropically etching down said insulating layer to form insulating layer spacers on the sidewalls of said trenches wherein the presence of said insulating layer spacers prevents metal diffusion into said first dielectric layer;
depositing a conductive barrier layer overlying said first dielectric layer and lining said trenches;
depositing a metal layer overlying said conductive barrier layer and filling said trenches;
polishing down said metal layer and said conductive barrier layer to confine said metal layer and said conductive barrier layer to said trenches and to thereby said damascene interconnects;
patterning said damascene interconnects to form via plugs in an upper portion of said damascene interconnects wherein said patterning comprises partially etching down said damascene interconnects, wherein a via mask overlies and protects portions of said damascene interconnects from said etching down, wherein a trench mask overlies and protects said first dielectric layer from metal contamination during said etching down, and wherein portions of said damascene interconnects partially etched down form conductive lines;
depositing a nonconductive barrier layer overlying said first dielectric layer, said conductive lines, and said via plugs;
and
depositing a second dielectric layer overlying said non-conductive barrier layer and filling gaps caused by said patterning of said copper layer to complete said metal interconnect level in the manufacture of said integrated circuit device.

8 more elements

A method to form copper interconnect levels in the manufacture of an integrated circuit device comprising:

depositing a first dielectric layer overlying a semiconductor substrate wherein said semiconductor substrate comprises all layers and devices formed prior to said depositing of said first dielectric layer and wherein said first dielectric layer may comprise a stack of dielectric materials;
patterning said first dielectric layer to form trenches for planned damascene interconnects;
depositing an insulating layer overlying said first dielectric layer and lining said trenches;
anisotropically etching down said insulating layer to form insulating layer spacers on the sidewalls of said trenches wherein the presence of said insulating layer spacers prevents metal diffusion into said first dielectric layer;
depositing a conductive barrier layer overlying said first dielectric layer and lining said trenches;
depositing a copper layer overlying said conductive barrier layer and filling said trenches;
polishing down said copper layer and said conductive barrier layer to confine said copper layer and said conductive barrier layer to said trenches and to thereby form said damascene interconnects;
patterning said damascene interconnects to form via plugs in an upper portion of said damascene interconnects wherein said patterning comprises partially etching down said damascene interconnects, wherein a via mask overlies and protects portions of said damascene interconnects from said etching down, wherein a trench mask overlies and protects said first dielectric layer from copper contamination during said etching down, and wherein portions of said damascene interconnects partially etched down form conductive lines;
depositing a nonconductive barrier Layer overlying said first dielectric layer, said conductive lines, and said via plugs;
and
depositing a second dielectric layer overlying said non-conductive barrier layer and filling gaps caused by said patterning of said copper layer to complete said metal interconnect level in the manufacture of said integrated circuit device.

8 more elements

A method to form copper interconnect levels in the manufacture of an integrated circuit device comprising:

depositing a first dielectric layer overlying a semiconductor substrate wherein said semiconductor substrate comprises all layers and devices formed prior to said depositing of said first dielectric layer and wherein said first dielectric layer may comprise a stack of dielectric materials;
patterning said first dielectric layer to form trenches for planned damascene interconnects;
depositing an insulating layer overlying said first dielectric layer and lining said trenches;
anisotropically etching down said insulating layer to form insulating layer spacers on the sidewalls of said trenches;
depositing a conductive barrier layer overlying said first dielectric layer and said insulating layer spacer, and lining said trenches;
depositing a copper layer overlying said conductive barrier layer and filling said trenches;
polishing down said copper layer and said conductive barrier layer to confine said copper layer and said conductive barrier layer to said trenches and to thereby form said damascene interconnects;
depositing a passivation layer overlying said damascene interconnects, said conductive barrier layer, said insulating layer spacers, and said first dielectric layer wherein the presence of said passivation layer overlying said first dielectric layer prevents copper diffusion into said first dielectric layer;
patterning said damascene interconnects to form via plugs in an upper portion of said damascene interconnects wherein said patterning comprises etching through said passivation layer and partially etching down said damascene interconnects, wherein a via mask overlies and protects portions of said damascene interconnects from said etching down, wherein a trench mask overlies and protects said first dielectric layer from copper contamination during said etching down, wherein the presence of said insulating layer spacers prevents copper diffusion into said first dielectric layer, and wherein portions of said damascene interconnects partially etched down form conductive lines;
depositing a nonconductive barrier layer overlying said first dielectric layer, said conductive lines, and said via plugs;
and
depositing a second dielectric layer overlying said non-conductive barrier layer and filling gaps caused by said patterning of said copper layer to complete said metal interconnect level in the manufacture of said integrated circuit device.

9 more elements

A method to form copper interconnect levels in the manufacture of an integrated circuit device comprising:

depositing a first dielectric layer overlying a semiconductor substrate wherein said semiconductor substrate comprises all layers and devices-formed prior to said depositing of said first dielectric layer and wherein said first dielectric layer may comprise a stack of dielectric materials;
patterning said first dielectric layer to form trenches for planned damascene interconnects;
depositing a conductive barrier layer overlying said first dielectric layer and lining said trenches;
depositing a copper layer overlying said conductive barrier layer and filling said trenches;
polishing down said copper layer and said conductive barrier layer to confine said copper layer and said conductive barrier layer to said trenches and to thereby form said damascene interconnects;
depositing a passivation layer overlying said damascene interconnects, said conductive barrier layer, and said first dielectric layer after said step of polishing down said copper layer and said barrier layer;
patterning said passivation layer and said damascene interconnects to form via plugs in an upper portion of said damascene interconnects wherein said patterning comprises partially etching down said damascene interconnects, wherein a via mask overlies and protects portions of said damascene interconnects from said etching down, wherein a trench mask overlies and protects said first dielectric layer from copper contamination during said etching down, wherein the presence of said passivation layer overlying said first dielectric layer prevents copper diffusion into said first dielectric layer, and wherein portions of said damascene interconnects partially etched down form conductive lines;
depositing a nonconductive barrier layer overlying said first dielectric layer, said conductive lines, and said via plugs;
and
depositing a second dielectric layer overlying said non-conductive barrier layer and filling gaps caused by said patterning of said copper layer to complete said metal interconnect level in the manufacture of said integrated circuit device.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/598,691Filed 21 Jun 2000
Granted: 5 Mar 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10W 20/0633
By forming conductive members before forming protective insulating material: using subtractive patterning of the conductive members
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias