Back to results
US 6,351,013 B1Granted
Low-K sub spacer pocket formation for gate capacitance reduction
AssigneeAdvanced Micro Devices, Inc.
InventorsScott Luning, David Wu, Khanh Tran
Life of this patent
Estimating the term…
Abstract
The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.
Claims6
A semiconductor device comprising:
- a semiconductor substrate;
- a dielectric layer formed on the semiconductor substrate;
- a gate electrode having an upper surface and side surfaces formed on the dielectric layer;
- first sidewall spacers, comprising a first material having a low dielectric constant, formed on the side surfaces of the gate electrode;
- a shallow source/drain region extending to a first depth below the surface of the semiconductor substrate;
- and
- a moderately or heavily doped source/drain region extending to a second depth greater than the first depths,
- wherein the first material has a dielectric constant of about 1.5 to about 3.5.
5 more elements
Dependencies are inferred from the claim text.