# US 6,350,993 B1 · High speed composite p-channel Si/SiGe heterostructure for field effect devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,350,993 B1 - Document ID: US6350993B1 - Status: Granted - Kind: B1 - Application number: 09/267,323 - Filed: 1999-03-12 - Granted: 2002-02-26 - Earliest claimed: 1999-03-12 - Assignees: International Business Machines Corporation - Inventors: Jack Oon Chu; Richard Hammond; Khalid EzzEldin Ismail; Steven John Koester; Patricia May Mooney; John A. Ott - Web page: https://patentgrep.com/patent/US6350993B1 ## CPC - H10D 30/473: {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT} - H10D 30/751: {having composition variations in the channel regions} - H10D 30/798: {being provided in or under the channel regions} - H10D 62/213: {Channel regions of field-effect devices} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer. ## Claims ### Claim 1 A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si1−xGex formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si1−xGex formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of undoped Si1−xGex formed epitaxially on said third layer, a fifth layer of Ge formed epitaxially on said fourth layer whereby said fifth layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a sixth layer of Si1−wGew formed epitaxially on said fifth layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said sixth layer is under compressive strain, and a seventh layer of Si1−xGex formed epitaxially on said sixth layer. ### Claim 2 (depends on 1) The layered structure of claim 1 further including an over-shoot layer, Si1−yGey, within the strain relief structure of said first layer having a Ge fraction y, where y=x+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer. ### Claim 3 (depends on 1) The layered structure of claim 1 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said fifth layer and an epitaxial Si1−wGew channel of said sixth layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone. ### Claim 4 (depends on 1) The layered structure of claim 1 wherein said fifth layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275°-350° C. where 2D growth of Ge films does occur. ### Claim 5 (depends on 1) The layered structure of claim 1 wherein the Ge content w may be graded within said sixth layer starting with a higher Ge content nearer said fifth layer and grading down in Ge content towards the upper surface of said sixth layer. ### Claim 6 (depends on 1) The layered structure of claim 1 wherein a spacer region comprises said third layer of strained Si and said fourth layer of relaxed Si1−xGex. ### Claim 7 (depends on 1) The layered structure of claim 1 wherein said third layer is under tensile strain and is commensurate having a thickness below its critical thickness with respect to said first layer at its interface with said second layer. ### Claim 8 (depends on 1) The layered structure of claim 1 wherein said second layer is a p-doped Si1−xGex layer formed below a channel region of said fifth and sixth layers and separated therefrom by said third layer of Si and said fourth layer of Si1−xGex, said second layer having a thickness in the range from 1 to 20 nm with a preferred thickness from 4 to 5 nm and having an electrically active donor dose in the range from 1 to 3×1012 cm−2. ### Claim 9 (depends on 1) A field-effect transistor structure consisting of the layered structure of claim 1, further comprising, electrical isolation regions created by the selective removal of at least said seventh through second layer, a Schottky gate electrode formed on said seventh layer, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode. ### Claim 10 (depends on 1) A field-effect transistor structure consisting of the layered structure of claim 1, further comprising, electrical isolation regions created by the selective removal of at least said seventh through second layer, a gate dielectric formed on said seventh layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode. ### Claim 11 A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si1−xGex formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si1−xGex formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of Ge formed epitaxially on said third layer whereby said fourth layer is under compressive strain and having a thickness less than its critical thickness with respect to said first layer, a fifth layer of Si1wGew formed epitaxially on said fourth layer wherein the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said fifth layer is under compressive strain, and a sixth layer of Si1−xGex formed epitaxially on said fifth layer. ### Claim 12 (depends on 11) The layered structure of claim 11 further including an over-shoot layer, Si1−yGey, within the strain relief structure of said first layer having a Ge fraction y, where y=+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer. ### Claim 13 (depends on 11) The layered structure of claim 11 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said fourth layer and an epitaxial Si1−wGew channel of said fifth layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone. ### Claim 14 (depends on 11) The layered structure of claim 11 wherein said fourth layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275-350° C. where 2D growth of Ge films does occur. ### Claim 15 (depends on 11) The layered structure of claim 11 wherein the Ge content w may be graded within said fifth layer starting with a higher Ge content nearer said fourth layer and grading down in Ge content towards the upper surface of said fifth layer. ### Claim 16 (depends on 11) The layered structure of claim 11 wherein a spacer region is a single layer structure comprised of said third layer wherein said third layer is strained Si. ### Claim 17 (depends on 11) The layered structure of claim 11 wherein said third layer is under tensile strain and is commensurate having a thickness below its critical thickness with respect to said first layer at its interface with said second layer. ### Claim 18 (depends on 11) The layered structure of claim 11 wherein said third layer Si may be substituted with a relaxed Si1−xGex layer with an adjustable thickness to allow the spacer thickness to be varied accordingly whereby the supply dose may be optimized for device applications as a function of temperature in the range from 0.4 to 425 K. ### Claim 19 (depends on 18) The layered structure of claim 18 wherein the supply layer of said second layer is formed and separated below the channel region of said fourth and fifth layers by said relaxed Si1−xGex layer. ### Claim 20 (depends on 11) The layered structure of claim 11 wherein said second layer is a p-doped Si1−xGex layer formed below a channel region of said fourth and fifth layers and separated therefrom by said third layer of Si. ### Claim 21 (depends on 11) A field-effect transistor structure consisting of the layered structure of claim 11, further comprising, electrical isolation regions created by the selective removal of at least said sixth through second layer, a Schottky gate electrode formed on said sixth layer, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode. ### Claim 22 (depends on 9) A field-effect transistor structure consisting of the layered structure of claim 9, further comprising, electrical isolation regions created by the selective removal of at least said sixth through second layer, a gate dielectric formed on said sixth layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode. ### Claim 23 A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si1−xGex formed epitaxially on said substrate where Ge fraction x is the range from 0.35 to 0.5, a second layer of Ge formed epitaxially on said first layer whereby said second layer is under compressive strain and having a thickness less than its critical thickness with respect to said first layer, a third layer of Si1−wGew formed epitaxially on said second layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said third layer is under compressive strain, a fourth layer of undoped Si1−xGex formed epitaxially on said third layer, a fifth layer of undoped Si formed epitaxially on said fourth layer, and a sixth layer of p-doped Si1−xGex formed epitaxially on said fifth layer. ### Claim 24 (depends on 23) The layered structure of claim 23 further including an over-shoot layer, Si1−yGey within the strain relief structure of said first layer having a Ge fraction y, where y=x+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer. ### Claim 25 (depends on 23) The layered structure of claim 23 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said second layer and an epitaxial Si1−wGew channel of said third layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone. ### Claim 26 (depends on 23) The layered structure of claim 23 wherein said second layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275°-350° C. where 2D growth of Ge films does occur. ### Claim 27 (depends on 23) The layered structure of claim 23 wherein the Ge content w may be graded within said third layer starting with a higher content nearer said second layer and grading down in Ge content towards the upper surface of said third layer. ### Claim 28 (depends on 23) The layered structure of claim 23 wherein a spacer region is a composite layer structure comprising said fifth layer of strained Si and said fourth layer of relaxed Si1−xGex. ### Claim 29 (depends on 23) The layered structure of claim 23 wherein said fifth layer is under tensile strain and is commensurate having a thickness below its critical thickness with respect to said first layer at its interface with said second layer. ### Claim 30 (depends on 23) The layered structure of claim 23 wherein the supply layer is a p-doped Si1−xGex layer of said sixth layer formed above a channel region of said second and third layers and is separated by a composite spacer structure of said fifth layer of Si and said fourth layer of Si1−xGex. ### Claim 31 (depends on 23) A field-effect transistor structure consisting of the layered structure of claim 23, further comprising, electrical isolation regions created by the selective removal of at least said sixth through second layer, a gate dielectric formed on said sixth layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode. ### Claim 32 A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si1−xGex formed epitaxially on said substrate where Ge fraction x is the range from 0.35 to 0.5, a second layer of Ge formed epitaxially on said first layer whereby said second layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a third layer of Si1−wGew formed epitaxially on said second layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said third layer is under compressive strain, a fourth layer of undoped Si1−xGex formed epitaxially on said third layer, and a fifth layer of p-doped Si1−xGex formed epitaxially on said fourth layer. ### Claim 33 (depends on 32) The layered structure of claim 32 further including an over-shoot layer, Si1−yGey, within the strain relief structure of said first layer having a Ge fraction y, where y=x+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer. ### Claim 34 (depends on 32) The layered structure of claim 32 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said second layer and an epitaxial Si1−wGew. channel of said third layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone. ### Claim 35 (depends on 32) The layered structure of claim 32 wherein said second layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275°-350° C. where 2D growth of Ge films does occur. ### Claim 36 (depends on 32) The layered structure of claim 32 wherein the Ge content w may be graded within said third layer starting with a higher content nearer said second layer and grading down in Ge content towards the upper surface of said third layer. ### Claim 37 (depends on 32) The layered structure of claim 32 wherein a spacer region is a single layer structure comprised of a relaxed Si1−xGex layer of said fourth layer. ### Claim 38 (depends on 32) The layered structure of claim 32 wherein said fourth layer of Si1−xGex may be substituted with a thin strained commensurate Si layer whereby a thin spacer thickness may be provided for a MODFET device. ### Claim 39 (depends on 38) The layered structure of claim 38 wherein said fifth layer is a p-doped Si1−xGex layer formed above a channel region of said second and third layers and separated therefrom by a thin strained commensurate Si layer. ### Claim 40 (depends on 32) The layered structure of claim 32 wherein said fifth layer is a p-doped Si1−xGex layer formed above a channel region of said second and third layers and separated therefrom by said fourth layer of Si1−xGex. ### Claim 41 (depends on 32) A field-effect transistor structure consisting of the layered structure of claim 32, further comprising, electrical isolation regions created by the selective removal of at least said fifth through second layer, a gate dielectric formed on said fifth layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.