Floating point square root and reciprocal square root computation unit in a processor

A method of computing a square root of a number X in a computing device comprising:

• computing a piece-wise quadratic approximation of the number X having a mantissa and an exponent in a plurality of parallel data paths using an equation of the form:
• {square root over (X)}=Ax2+Bx+C, the computing operation including:
• accessing the A, B, and C coefficients from a storage;
• squaring the x term of the number X to obtain an x2 term;
• multiplying the x2 term times the coefficient A to obtain an Ax2 term;
• multiplying the x term times the coefficient B to obtain a Bx term;
• summing the Ax2 term, the Bx term, and the C term to form an approximation result;
• shifting the exponent right;
• and
• multiplying the approximation result by a correction constant.

A computation unit comprising:

• a multiplier;
• an adder coupled to the multiplier;
• a connection to a storage, the storage storing coefficients for computing a piece-wise quadratic approximation;
• and
• a control logic controlling the adder, the multiplier, and access of the storage, the control logic controlling computation of a piece-wise quadratic approximation of the floating point number X using an equation of the form:
• 1/{square root over (X)}=Ax2+Bx+C;
• a shifter for shifting the result exponent right by one bit;
• and
• error correcting logic for correcting an error that occurs when an asserted bit in the result exponent is discarded by the shifting operation, the correcting operation including multiplying the computed result by a correction constant.