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US 6,347,062 B2Granted
Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKoji Nii, Atsushi Miyanishi
Life of this patent
Estimating the term…
Abstract
In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to bit lines. Two access gates are located in one P-well area and two access gates are located in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.
Claims27
A semiconductor memory device comprising:
- a semiconductor substrate;
- a first word line and a second word line;
- a first positive-phase bit line and a second positive-phase bit line;
- a first negative-phase bit line and a second negative-phase bit line;
- a first CMOS inverter having a first N-channel MOS transistor, a first P-channel MOS transistor, and input and output terminals;
- a second CMOS inverter having a second N-channel MOS transistor, a second P-channel MOS transistor, and input and output terminals, wherein said input terminal of said second CMOS inverter is connected to said output terminal of said first CMOS inverter as a first memory node, and said output terminal of said second CMOS inverter is connected to said input terminal of said first CMOS inverter as a second memory node;
- a third N-channel MOS transistor having a gate that is connected to said first word line, having a drain that is connected to said first positive-phase bit line, and having a source that is connected to said first memory node;
- a fourth N-channel MOS transistor having a gate that is connected to said first word line, having a drain that is connected to said first negative-phase bit line, and having a source that is connected to said second memory node;
- a fifth N-channel MOS transistor having a gate that is connected to said second word line, having a drain that is connected to said second positive-phase bit line, and having a source that is connected to said first memory node;
- and
- a sixth N-channel MOS transistor having a gate that is connected to said second word line, having a drain that is connected to said second negative-phase bit line, and having a source that is connected to said second memory node, wherein said first and second P-channel MOS transistors are located in an N-well area of said semiconductor substrate, said first, third, and fifth N-channel MOS transistors are located in a first P-well area of said semiconductor substrate, and said second, fourth, and sixth N-channel MOS transistors are located in a second P-well area of said semiconductor substrate.
8 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- a first word line;
- a second word line;
- a first positive-phase bit line;
- a first negative-phase bit line;
- a second positive-phase bit line;
- a first CMOS inverter including a first N-channel MOS transistor, a first P-channel MOS transistor, and input and output terminals;
- a second CMOS inverter including a second N-channel MOS transistor, a second P-channel MOS transistor, and an input terminal connected to said output terminal of said first CMOS inverter as a first memory node, an output terminal connected to an input terminal of said first CMOS inverter as a second memory node;
- a third N-channel MOS transistor that has a gate connected to said first word line, a drain connected to said first positive-phase bit line, and a source connected to said first memory node;
- a fourth N-channel MOS transistor that has a gate connected to said first word line, a drain connected to said first negative-phase bit line, and a source connected to said second memory node;
- a fifth N-channel MOS transistor that has a gate connected to said first memory node;
- and
- a sixth N-channel MOS transistor that has a gate connected to said second word line, a drain connected to said second positive-phase bit line, and a source connected to a drain of said fifth N-channel MOS transistor, wherein said first and second P-channel MOS transistors are located in an N-well area of said semiconductor substrate, said first and third N-channel MOS transistors are located in a first P-well area of said semiconductor substrate, and said second, fourth, fifth, and sixth N-channel MOS transistors are located in a second P-well area of said semiconductor substrate.
10 more elements
Dependencies are inferred from the claim text.