Apparatus and method for capacitance multiplication

Abstract

A capacitance multiplier network embodying the invention includes a first resistor, R1, connected between a first node and an intermediate node and a first capacitor, C1, connected between the intermediate node and a point of reference potential. A unity gain amplifier has an input connected to the intermediate node and its output is connected via a second resistor, R2, to the first node. The unity gain amplifier ensures that the voltage drop across the second resistor is equal to the voltage drop across the first resistor. The effective capacitance, Ce, of the network is equal to C1 times [R1+R2]/R2. Thus, by making R1 larger than R2, Ce is much large than the capacitance of C1. The capacitance multiplier network is well suited for use in phase locked loop circuits and enables the integration of a very dense circuit on the same IC chip.

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