Device code recognizing circuit

Abstract

A device code recognizing circuit includes a microprocessor forming an array having input pins and output pins and a code generation circuit connected to the microprocessor. The code generation circuit includes signal input terminals connected to input pins of the array and signal output terminals connected to I/O terminals of the microprocessor. The signal output terminals are sequentially and selectively set to one of low level condition and high impedance condition. The input pins of the microprocessor to which the signal input terminals of the code generation circuit are connected serially read signals from the code generation circuit for provision the signals to the microprocessor to form a device code associated therewith.

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