Processor with internal register for peripheral status

Abstract

One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register. This apparatus includes a communication channel coupled to a central processing unit and a number of peripheral devices. A status register is coupled with the central processing unit to store status information for the peripheral devices. An updating circuit is located within the core logic unit and is coupled between the communication channel and the status register. This updating circuit includes a mechanism to update the status register in response to signals containing status information received from the peripheral devices through the communication channel.

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