Word line driving circuit for semiconductor memory device

Abstract

A hierarchical word line driving circuit for a semiconductor memory device can reduce a sub-threshold voltage leakage current because a sub-word line is disabled at a back bias voltage, overcome a layout penalty because an additional NMOS transistor for preventing the sub-word line from floating is not employed, and sufficiently obtain a line pitch passing above the sub-word line. The hierarchical word line driving circuit for the semiconductor memory device includes: a main word line driver including a transmission gate for selectively outputting a main word line signal, a selective latch unit for selectively latching and outputting the main word line signal selectively transmitted by the transmission gate, and a level shift unit for outputting an output from the selective latch unit or a back bias voltage according to a block selection signal and the main word line signal; and a sub-word line driver controlled according to an output from the main word line driver, for driving a sub-word line by using an inputted lower coding signal or a ground voltage.

Claims aren’t available for this document.