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An integrated circuit memory device including at least one memory bank with the memory bank being logically partitioned into even and odd portions thereof. Even and odd data buses are provided which are selectively couplable to the even and odd portions of the memory banks respectively for placing read data thereon by means of corresponding first multiplexers in response to a first control signal. A read pipeline sorting block is coupled to the even and odd data buses for selectively applying the read data on the even data bus to either of a rising or falling edge data output bus and the read data on the odd data bus to an opposite one of the rising or falling edge data output buses. In a particular embodiment disclosed herein, the memory device may further include a write pipeline sorting block coupled to the rising and falling edge data buses for receiving write data thereon, the write pipeline sorting block selectively applies the write data on the rising edge data bus to either of the even or odd data buses and the write data on the falling edge data bus to an opposite one of the even or odd data buses. The integrated clocking latency and multiplexer control technique for DDR SDRAM device data paths which has been particularly disclosed completely integrates the clocking, control of the various input/output (“I/O”) configurations and implementation of various clocking latencies.
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