Clock synchronization semiconductor memory device sequentially outputting data bit by bit

Abstract

A semiconductor integrated circuit is provided with a plurality of selectors, each of which is connected to a corresponding one of a plurality of data lines through which bit data read out from a corresponding one of a plurality of cell array blocks is transmitted, wherein a selector control circuit controls selection operations of the selectors based on a control clock so that the selectors select and output readout data in the order in which the bit data are read out from the corresponding cell array blocks.

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