Dynamic memory device performing stress testing

Abstract

A dynamic memory device having a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells disposed at intersections thereof. The dynamic memory device includes a data bus and sense amplifiers. The data bus is connected a write amplifier. The sense amplifiers are provided to each of the bit line pairs, for amplifying voltage between the bit line pairs. In a stress testing mode, a plurality of the bit line pairs are commonly connected to the data bus, the write amplifier applies high and low voltages to the simultaneously connected bit line pairs, and thereafter the sense amplifiers associated with the selected bit line pairs are activated.

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