Semiconductor memory device having a redundancy construction

Abstract

A semiconductor memory device includes a plurality of column groups (memory blocks M1 to M9), a plurality of column selection circuits and a plurality of read/write circuits disposed in correspondence with the plurality of column groups, a redundancy selection circuit that selects connection to the read/write circuit by shifting the connection, and input/output circuits that selectively connect an input/output node of the redundancy selection circuit with the data input/output line.

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