Semiconductor memory device having redundant circuit

Abstract

A semiconductor memory device includes word lines, normal bit lines, a redundant bit line, and normal memory cells for storing data and each of which is coupled to one of the word lines and to one of the normal bit lines. The device also includes redundant memory cells each of which is coupled to one of the word lines and to the redundant bit line. The device further includes a coincidence circuit that receives a first address signal, indicating an address of one of the normal bit lines, and a second address signal, indicating an address of one of the normal bit lines to which a defective memory cell is coupled, and which selects the redundant bit line when the first address signal coincides with the second address signal. A logic circuit included in the device also receives the first address signal and the second address signal and selects one of the normal bit lines according to the first address signal, but is inhibited from selecting the normal bit line coupled to the defective memory cell identified by the second address signal.

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