Semiconductor memory device having reference potential generating circuit

Abstract

A test mode reference potential generating circuit outputs a reference potential from an output node by activation of a test mode signal. When a sample signal is in an activated state, a transfer gate is turned on, and a capacitor stores the reference potential. When the test is being conducted, the transfer gate is turned off by inactivation of the sample signal, and thus the reference potential stored in the capacitor is output from a node. Thus, the semiconductor memory device according to the present invention can generate a stable reference potential during the test mode.

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