Abstract
Column signals CL1˜CLm generated in a Y decoder circuit 31 are selectively output to a sub-register block 10S or a resister block 10R, based on enabling signals SEN and REN. Then, write-in data is stored in the sub-register block 10S or the resister block 10R or read-out data is obtained from the sub-register block 10S or the resister block 10R. By structuring in this way, it is possible to reduce the scale of a circuit of a semiconductor device and lessen the chip size.
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