Semiconductor memory device and method for reading data

Abstract

The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit 7 as a latch pulse SAL0A, and to a second latch group within the latch circuit 7 as a latch pulse SAL1A, respectively. Based on a control signal YS0˜YS31 input from a column decoder circuit 11, a Y selector 12 is connected to a sense amplifier circuit 8 via Y switches connected to the corresponding digit lines. The sense amplifier circuit 8 comprises 256 sense amplifiers, and performs data evaluations of the signal YD0˜signal YD127 from the Y selector. A latch circuit 7 latches a data signal DT0˜data signal DT127 from the sense amplifier circuit 8 into a first latch group and a second latch group via latch signals SAL0 and SAL1 respectively.

Claims aren’t available for this document.