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A semiconductor memory device is provided that is capable of increasing a data processing speed and the efficiency of a data input and output pin. A method is also provided for controlling the read and write of such a device. A data first-in first-out (FIFO) circuit temporarily stores write data when a read command is received during a write operation and outputs the stored write data to the memory cell array after a read operation is completed. An address FIFO circuit temporarily stores addresses corresponding to the write data when the read command is received during the write operation and outputs the stored addresses to the memory cell array after the read operation is completed. A control signal generator generates a plurality of control signals for controlling the data FIFO circuit and the address FIFO circuit in response to a write command and the read command. When the addresses received during the read operation coincide with the addresses stored in the address FIFO circuit, data is not output from the memory cell array, but instead, the write data stored in the data FIFO circuit is output. The number of write data items stored in the data FIFO circuit and the number of addresses stored in the address FIFO circuit vary according to the column address strobe (CAS) latency of the semiconductor memory device.
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