Memory circuit and method of using same

Abstract

The present invention provides a flash memory circuit having enhanced endurance properties. In a preferred embodiment, a differential flash memory cell and differential correlated double sampling sense amplifier are provided wherein a reduced charge differential on the floating gates of the memory cell are made possible and detectable by using a highly sensitive sense amplifier. A differential flash memory cell operating in the sub-threshold region is connected to a differential correlated double sampling sense amplifier to allow for charge differentials of less than 1.5×10−8 coulombs/cm2 between the two floating gates of each memory cell. This reduction in required charge greatly increases the long-term reliability and endurance of the memory cell, resulting in flash memory circuits which are capable of being used for over 109 cycles.

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