Integrated power circuit with reduced parasitic current flow

Abstract

Presented is an integrated circuit structure having a power transistor in a first well and control circuitry in another well. Between the power and control regions is an intermediate region including a biaging circuit secured to prevent flow of parasitic current from the wells into the substrate by biasing the intermediate region at a value of potential which is tied to the value of potential of the first well. The biasing circuit can include a bipolar transistor.

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