System and method for merging multiple outstanding load miss instructions

Abstract

Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

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