Memory control device with split read for ROM access

Abstract

In a computer memory system, memory access operations are significantly enhanced by employing a data path between the read only memory (ROM) and the system processor that is separate and independent from the data path or paths between the system processor and the random access memory (i.e., RAM or DRAM). The separate ROM data path includes a full cache line buffer which stores the ROM data until the system data bus is available to transport the ROM data. With a separate ROM data path, that includes a full cache line buffer, memory access operations are more efficiently conducted because a RAM access (i.e., a read or write operation) and a ROM access (i.e., a read operation) can be executed concurrently.

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