US 6,336,087 B1 · Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging

Abstract

Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.

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Facts

Application

09/122,493Filed 24 Jul 1998

Published

US 2001/0011212 A12 Aug 2001

Granted

1 Jan 2002

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3308
Design verification, e.g. functional simulation or model checking: using simulation

Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging

Life of this patent

Abstract

Claims0

Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging

Life of this patent

Abstract

Claims0