US 6,335,896 B1 · Dynamic random access memory

Abstract

A capacitor memory data storage system of reading, writing and refreshing which uses short bit line segments separated by pass transistors to allow smaller capacitors and faster speeds than the prior art.

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Facts

Application

08/792,419Filed 3 Feb 1997

Granted

1 Jan 2002

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 1/047
Of capacitors having potential barriers, e.g. varactors: of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C 11/4074
For memory cells of the field-effect type: power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage…

Dynamic random access memory

Life of this patent

Abstract

Claims0

Dynamic random access memory

Life of this patent

Abstract

Claims0