Semiconductor storage device and system using the same

Abstract

The present invention relates to a semiconductor storage device in which data retention current consumption can be reduced. This device comprises memory cells, an internal power supply circuit for supplying an internal voltage HVC to the memory cells, transistors for halting the internal power supply circuit, and a switch circuit (transistors) for selectively supplying one of the internal voltage HVC or an externally supplied voltage HVC_EXT to the memory cells. When the memory cells are in a stand-by state (SLEEP=1) and are not engaged in a refresh operation, the internal power supply circuit is halted, and the externally supplied voltage HVC_EXT is supplied to the memory cells.

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