Semiconductor memory device

Abstract

A semiconductor memory device is disclosed that is capable of outputting in the fastest possible time the first of serial data that are read in bursts, despite the increase in capacity of a memory cell array. In this semiconductor memory device, for a single address access, a plurality of bits of serial data are read in a burst from a memory sub-array that is made up by memory cell arrays 11Uo and 11Ue or memory cell arrays 11Le and 11Lo. In order that the serial data that are read first are the data of bit 0 regardless of the operation mode of the semiconductor memory device, each individual memory sub-array is divided between portions for even data and portions for odd data and the even memory cell arrays 11Ue and 11Le in which the data of bit 0 are stored are arranged closer to the data amplifier than the odd memory cell arrays 11Uo and 11Lo. The maximum length of I/O lines that are used in reading even data is therefore about half that of the maximum length of I/O lines that are used in reading odd data.

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