Nonvolatile semiconductor memory device capable of erasing blocks despite variation in erasing characteristic of sectors

Abstract

A power generating portion generates an erasing potential for an erasing operation with respect to information stored in a memory cell and variably generates a first potential applied to the selected memory cell and a second potential applied to the non-selected memory cell during a reading operation. A chip control portion selectively applies an erasing potential to every block to be erased. At the time, the chip control portion applies the first potential to any one of sectors in the block to be erased and also applies the second potential, which has been updated such that none of the memory cells belonging to the block to be erased is conductive, to the remaining sectors in the block to be erased for performing an erasing verify operation.

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