Wavefront technology mapping
AssigneeInternational Business Machines Corporation
InventorsMahesh A. Iyer, Leon Stok, Andrew J. Sullivan
Life of this patent
Estimating the term…
Abstract
A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.
Claims11
A method for optimizing a cost function in technology mapping in logic synthesis for directed acyclic graphs, comprising the steps of:
- partitioning a circuit into a plurality of slices, each slice representing a subcircuit, each subcircuit having a netlist, a head boundary closer to primary outputs, and a tail boundary closer to primary inputs of the circuit;
- matching each net in each subcircuit by advancing from the head boundary of the first subcircuit through each partitioned subcircuit in the direction of primary outputs while generating and implementing cell matches;
- covering each net in each subcircuit by advancing from the tail boundary of the first subcircuit through each partitioned subcircuit in the direction of primary outputs while performing timing analysis and selecting matches having optimal times;
- and
- discarding portions of subcircuits not selected.
A stored program device readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for optimizing a cost function in logic synthesis, said method steps comprising:
- partitioning a circuit into a plurality of slices, each slice representing a subcircuit, each subcircuit having a netlist, a head boundary closer to primary outputs, and a tail boundary closer to primary inputs of the circuit;
- matching each net in each subcircuit by advancing from the head boundary of the first subcircuit through each partitioned subcircuit in the direction of primary outputs while generating and implementing cell matches;
- covering each net in each subcircuit by advancing from the tail boundary of the first subcircuit through each partitioned subcircuit in the direction of primary outputs while performing timing analysis and selecting matches having optimal times;
- and
- discarding portions of subcircuits not selected.
A device having computer readable program code embodied thereon for causing the computer to optimize a cost function in logic synthesis, the program code in the device comprising:
- partitioning a circuit into a plurality of slices, each slice representing a subcircuit, each subcircuit having a netlist, a head boundary closer to primary outputs, and a tail boundary closer to primary inputs of the circuit;
- matching each net in each subcircuit by advancing from the head boundary of the first subcircuit through each partitioned subcircuit in the direction of primary outputs while generating and implementing cell matches;
- covering each net in each subcircuit by advancing from the tail boundary of the first subcircuit through each partitioned subcircuit in the direction of primary outputs while performing timing analysis and selecting matches having optimal times;
- and
- discarding portions of subcircuits not selected.
Dependencies are inferred from the claim text.