Decoding circuit and information processing apparatus
AssigneeHitachi, Ltd.
InventorsHideki Sawaguchi, Akihiko Hirano, Seiichi Mita, Terumi Takashi
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AssigneeHitachi, Ltd.
InventorsHideki Sawaguchi, Akihiko Hirano, Seiichi Mita, Terumi Takashi
Estimating the term…
A maximum likelihood decoding circuit is arranged to reduce power consumption through the effect of a Viterbi algorithm. A plurality of storing elements located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks in a manner to correspond to the combination (state) of intracode interferences. The outputs from the storing elements are again applied into the inputs of the corresponding storing elements contained in the same storing element block through path history selecting circuits. Each of the storing blocks is periodically started on the input timing of a receiving signal at each processing time point by starting signals (pointers) outputted from a starting signal (pointer) generated circuit. A storing element block output circuit and storing element block output terminals are provided in each of the storing element blocks so that a path memory circuit output may be outputted through an OR circuit.
A decoding circuit for estimating a maximum likelihood sequence through the effect of the Viterbi algorithm, wherein an average power consumption or an integrating power consumption of said decoding circuit is changed according to the difference of a decoding input signal sequence to be inputted into said decoding circuit and during a given decoding period, and an average power consumption or an integrating power consumption given in the case of continuously giving a zero input signal sequence and decoding said sequence is larger than an average power consumption or an integrating power consumption given in the case of giving any noiseless input signal sequence, for meeting a given constraint condition regulated in said decoding input signal sequence and decoding said sequence.
A decoding circuit for estimating a maximum likelihood sequence through the effect of the Viterbi algorithm, comprising:
A decoding circuit for estimating a maximum likelihood sequence through the effect of the Viterbi algorithm by using a survivor path sequence storing circuit for storing a desired number of decoding input signal sequences, comprising:
A decoding circuit for estimating a maximum likelihood sequence through the effect of the Viterbi algorithm by using a survivor path sequence storing circuit for storing a desired number of decoding input signal sequences, comprising:
Dependencies are inferred from the claim text.