Testable integrated circuit, integrated circuit design-for-testability method, and computer-readable medium storing a program for implementing the design-for-testability method

A design-for-testability method for an integrated circuit having a sequential circuit describable as a finite state machine having a finite number of states, including a reset state, said design-for-testability method comprising:

• a logic circuit generating step for generating a logic circuit comprising a state register and a combinational circuit by logic synthesis of a finite state machine described at a register transfer level;
• a test pattern set generating step for generating a set of test patterns by applying a specific test generation algorithm to said combinational circuit using an assumption that state register states are controllable and observable;
• a transition-resistant valid state detection step for detecting as a transition-resistant valid state a valid state where the transition sequence required to select that state exceeds a predefined length, or the processing time required to determine a transition sequence for selecting that state exceeds a predefined limit,
• said valid state being defined as any state directly selectable by the finite state machine from a reset state thereof;
• a state transition path determining step for determining a state transition path passing all transition-resistant valid states and all invalid states indicated by a test pattern part corresponding to a state register setting in each test pattern of a test pattern set,
• said invalid state being defined as any state expressible by the state register but not directly selectable from the reset state of the finite state machine;
• and
• an adding step for generating an invalid-state generation logic circuit for changing to all selectable invalid states and transition-resistant valid states on the state transition path, and adding said invalid-state generation logic circuit to the sequential circuit.

A computer-readable recording medium for recording a program for designing a testable integrated circuit having a sequential circuit describable as a finite state machine having a finite number of states, including a reset state, said computer-readable recording medium recording a program for executing steps including:

• a logic circuit generating step for generating a logic circuit comprising a state register and a combinational circuit by logic synthesis of a finite state machine described at a register transfer level;
• a test pattern set generating step for generating a set of test patterns by applying a specific test generation algorithm to said combinational circuit using an assumption that state register states are controllable and observable;
• a transition-resistant valid state detection step for detecting as a transitionresistant valid state a valid state where the transition sequence required to select that state exceeds a predefined length, or the processing time required to determine a transition sequence for selecting that state exceeds a predefined limit,
• said valid state being defined as any state directly selectable by the finite state machine from a reset state thereof;
• a state transition path determining step for determining a state transition path passing all transition-resistant valid states and all invalid states indicated by a test pattern part corresponding to a state register setting in each test pattern of a test pattern set,
• said invalid state being defined as any state expressible by the state register but not directly selectable from the reset state of the finite state machine;
• and
• an adding step for generating an invalid-state generation logic circuit for changing to all selectable invalid states and transition-resistant valid states on the state transition path, and adding said invalid-state generation logic circuit to the sequential circuit.